Optical and Electrical Testing of Latchup in I/O Interface Circuits
نویسندگان
چکیده
Backside light emission and electrical measurements were used to evaluate the susceptibility to latchup of externally cabled I/O pins for a 0.13 μm technology generation [1,2] test chip, which was designed in a flip-chip package. Case studies of several Inputs/Outputs (I/Os) are shown along with conclusions regarding layout and floorplanning to ensure the robustness to various types of latchup trigger events.
منابع مشابه
Design optimization of ESD protection and latchup prevention for a serial I/O IC
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